ASML布局混合键合设备,专利与路线图暗示D2W工具研发
ASML Is Building a Hybrid Bonding Tool!
深度解析ASML跨界半导体后道封装设备的战略意图与技术路径,揭示了算力硬件产业链上游的关键变量,值得关注。
ASML has not announced anything yet, but its patent filings, a news report and its own roadmap all suggest so. We believe it will start with a die-to-wafer (D2W) hybrid bonding (HB) tool. This is harder to build than wafer-to-wafer but is where ASML could gain an edge. We see the move as a natural extension of ASML’s vertical integration, and one that should strengthen its customer ties.
ASML 尚未宣布任何消息,但其专利申请、新闻报道以及自身路线图均暗示了这一点。我们认为它将首先推出一款晶圆到芯片(D2W)混合键合(HB)设备。该设备的制造难度高于晶圆对晶圆(W2W),但 ASML 有望在此获得优势。我们将此举视为 ASML 垂直整合的自然延伸,并认为这将加强其与客户的联系。
In this article we unpack the tool’s design end to end, starting with patent filings. What makes it unique is that it runs on a track. That changes how the tool and the dies move: each die rides its own holder past the process stations, and the tools get closer at each station to process the dies. The track’s independent shuttles also lift station utilization, save on duplicate tooling, and enable heterogeneous integration.
在本文中,我们从专利申请入手,全面解析该设备的设计。其独特之处在于它运行于涂胶显影机(track)上。这改变了设备和芯片的移动方式:每个芯片都搭载在自己的载体上,依次经过各个工艺站,而设备在各站点靠近以处理芯片。涂胶显影机独立的穿梭器还能提高各站的利用率,节省重复的设备投入,并实现异构集成。
We believe ASML could gain an edge in alignment accuracy and particle control for Hybrid Bonding. These are the two factors that set bonding yield. And ASML has expertise in solving the same problems in lithography.
我们认为 ASML 有望在混合键合的对准精度和颗粒控制方面获得优势。这两者是决定键合良率的关键因素。而 ASML 在光刻领域解决同类问题方面拥有专业知识。
Despite the advantages, ASML still needs to solve challenges around feed-forward metrology, the die-to-wafer contact, the modification of the non-bonding tools so they can process dies on the track, and keeping the whole loop clean.
尽管具有这些优势,ASML 仍需解决前馈量测、芯片到晶圆的接触、为非键合工具改造以便其在涂胶显影机上处理芯片,以及保持整个流程洁净等挑战。
We expect advanced logic, where D2W already runs in volume, to adopt ASML’s D2W HB tool first. This is bad news for Besi. Logic accounts for most of Besi’s HB business today concentrated at TSMC and Intel. ASML has been working with both for more than two decades and just announced a joint photomask initiative in September. We won’t be surprised to see a similar move in the back end process. Besi’s HBM prospects are also weakening. Korean challengers are catching up, in addition to an HBM adoption that we expect to slip to 2029 or beyond.
我们预计先进逻辑芯片领域将率先采用 ASML 的 D2W HB 设备,因为 D2W 在该领域已实现量产。这对 Besi 来说是个坏消息。目前 Besi 的 HB 业务主要集中在台积电和英特尔,而这部分业务主要源于逻辑芯片。ASML 已与这两家公司合作超过二十年,并于今年九月宣布了一项联合光掩模倡议。如果后端工艺出现类似动向,我们也不会感到惊讶。Besi 的高带宽内存(HBM)前景也在减弱。韩国竞争对手正在迎头赶上,此外,我们预计 HBM 的普及时间将推迟至 2029 年或更晚。
ASML is Building a Hybrid Bonder
ASML 正在打造混合键合设备
We did a deep dive on hybrid bonding in 2024, and we still see it as the most transformative innovation in semiconductor manufacturing since EUV. Wafer-to-wafer (W2W) hybrid bonding (HB) is already in volume in image sensors and 3D NAND, and DRAM makers will be next. Die-to-wafer (D2W) HB is moving slower, because the industry still lacks mature tools that combine satisfying alignment accuracy and throughput (our check indicates upper bound in current applications is only one wafer per hour), which keeps cost per die high. Today D2W runs in volume only in logic: AMD has shipped hybrid-bonded V-Cache since 2022, and TSMC’s SoIC bonds at about 6um pitch today and targets 4.5um around 2029. The market expected HBM to become the big D2W volume driver from 2028. However, our view is different: we believe HBM will not adopt D2W HB before 2029, if at all.
我们在2024年深入研究了混合键合(hybrid bonding),并仍然认为它是自极紫外光刻(EUV)以来半导体制造领域最具变革性的创新。晶圆对晶圆(W2W)混合键合(HB)已在图像传感器和3D NAND中实现量产,DRAM厂商将是下一个采用者。芯片对晶圆(D2W)HB的进展较慢,因为行业仍缺乏能将令人满意的对准精度与吞吐量相结合的设备(我们的调查显示,当前应用中的上限仅为每小时一片晶圆),这使得每颗芯片的成本居高不下。目前,D2W仅在逻辑芯片领域实现量产:AMD自2022年起已出货采用混合键合的V-Cache产品,台积电的SoIC技术目前的键合间距约为6微米,目标是在2029年左右达到4.5微米。市场曾预期高带宽内存(HBM)将从2028年开始成为D2W大规模量产的主要驱动力。然而,我们的观点不同:我们认为HBM在2029年之前甚至可能永远不会采用D2W HB。
Besi has led D2W and is the only supplier with tools in volume production. Everyone else is still trying to get a first tool qualified. But we believe the situation will soon change, because ASML is building a D2W hybrid bonding tool. Management hasn’t announced anything yet. But the company filed 27 bonding patent families between December 2022 and November 2024, most of them D2W, and the true count is likely higher because filings made after November 2024 are not yet public. The Elec also reported in March that ASML had started the architecture design of a hybrid bonder with Prodrive Technologies and VDL ETG.
Besi在D2W领域处于领先地位,是唯一拥有量产设备的供应商。其他所有人仍在努力使其首台设备通过认证。但我们相信情况很快会改变,因为ASML正在开发一款D2W混合键合设备。管理层尚未宣布任何消息。但该公司在2022年12月至2024年11月期间提交了27个键合专利族,其中大多数是D2W相关的,实际数量可能更高,因为2024年11月之后提交的申请尚未公开。《电子时报》(The Elec)也在3月报道称,ASML已与Prodrive Technologies和VDL ETG合作启动了混合键合机的架构设计。
In the anchor filing (WO2025201788A1), ASML drew how its bonding flow works. Interestingly, the system looks nothing like a traditional D2W bonder (see Advanced Packaging Part 5 for how those work). Instead of a bond head picking each die off a diced wafer and placing it, ASML moves single dies on independent holders around a track (Fig 1). Each die passes inspection, cleaning, plasma activation and metrology (topography, leveling and alignment) stations before it reaches the bonding station where the chuck lifts the bottom wafer up to meet the die. We unpack the design in the sections below.
在基础专利申请(WO2025201788A1)中,ASML展示了其键合流程的工作原理。有趣的是,该系统与传统D2W键合机(参见“先进封装第5部分”了解其工作原理)截然不同。ASML并非使用键合头从切割后的晶圆上拾取每个芯片并进行放置,而是将单个芯片放在独立的载体上沿轨道移动(图1)。每个芯片在到达键合站之前,会依次经过检测、清洗、等离子体活化和计量(形貌、平整度和对准)工位,随后键合站的卡盘会将底部晶圆抬起以迎接芯片。我们将在下文详细解析该设计。
Fig 1: ASML’s track-based D2W bonder, SA annotated and simplified
图1:ASML基于轨道的D2W键合机,SA进行了标注和简化
Source: ASML; SemiAnalysis Wafer Fabrication Equipment Model
来源:ASML;SemiAnalysis晶圆制造设备模型
ASML could be building a W2W hybrid bonding tool as well. According to a patent analysis by Inha University, ASML is likely building W2W HB equipment on its TWINSCAN platform, leaning on its wafer overlay accuracy. We focus on the D2W machine in this note, because it is the harder tool to build and the one where ASML could gain a real edge.
ASML 可能也在研发 W2W(晶圆对晶圆)混合键合设备。根据韩国仁荷大学的一项专利分析,ASML 很可能正基于其 TWINSCAN 平台开发 W2W HB 设备,并依托其晶圆套刻精度优势。本笔记重点关注 D2W(裸片对晶圆)设备,因为它是更难制造的设备,也是 ASML 可能获得真正竞争优势的领域。
…as Part of its Vertical Integration Initiative
……作为其垂直整合倡议的一部分
We believe this is a continuation of ASML’s effort to integrate vertically and tighten customer relationships. ASML bought Cymer for its light source in 2013, HMI for e-beam inspection in 2016 and Berliner Glas for optics modules in 2020. It shipped its first back-end product, the XT:260 i-line packaging scanner, in 3Q25. And most recently, ASML announced joint initiatives with TSMC, Intel Foundry and Samsung to move the industry from 6-inch to 12-inch photomasks for High NA EUV.
我们认为这是 ASML 持续努力进行垂直整合并加强客户关系的表现。ASML 于 2013 年收购 Cymer 以获取光源技术,2016 年收购 HMI 以获取电子束检测能力,并于 2020 年收购 Berliner Glas 以获取光学模块。ASML 于 2025 年第三季度交付了其首款后端产品——XT:260 i-line 封装扫描仪。最近,ASML 宣布与台积电、英特尔代工和三星开展联合倡议,推动行业从 6 英寸光掩膜转向用于 High NA EUV 的 12 英寸光掩膜。
Building a bonder would be a natural next step. In fact, ASML’s own roadmap already puts bonding inside the front-end flow. Its 2024 Investor Day listed W2W and D2W hybrid bonding for NAND, DRAM and logic (Fig 2). And a July 2024 filing shows how the bonder and the scanner would work together by sharing die position data. Today a scanner printing on a bonded wafer must pre-align and coarse-align every die before it can expose. In ASML’s design the bonder already knows where it put each die and hands that map (a “coordinate system” in the filing) to the scanner, which checks a few marks and exposes. Customers get faster lithography on bonded wafers, and ASML gets to sell the bonder and the scanner as a pair.
研发键合机将是顺理成章的下一步。事实上,ASML 自身的技术路线图已将键合工艺纳入前端流程。其在 2024 年投资者日上列出了针对 NAND、DRAM 和逻辑芯片的 W2W 和 D2W 混合键合方案(图 2)。此外,一份 2024 年 7 月的文件展示了键合机如何通过与扫描仪共享裸片位置数据来协同工作。目前,在已键合晶圆上进行光刻的扫描仪必须在曝光前对每个裸片进行预对准和粗对准。而在 ASML 的设计中,键合机已经知道每个裸片的放置位置,并将该映射关系(文件中称为“坐标系”)交给扫描仪,扫描仪只需检查几个标记即可进行曝光。客户可以在已键合晶圆上实现更快的光刻速度,而 ASML 则可以将键合机和扫描仪作为一套组合进行销售。
Fig 2: ASML’s map of front-end 3D integration
图 2:ASML 的前端 3D 集成路线图
Source: ASML Investor Day, 14-Nov-2024
来源:ASML 投资者日,2024 年 11 月 14 日
We expect advanced logic to be the first adopter. Logic is where D2W HB already runs in volume, and where the alignment requirement keeps tightening. TSMC calls overlay “always the biggest challenge” for SoIC. As its HB pitch moves from 6um to 4.5um by 2029, the placement accuracy requirement will tighten further. ASML is strong in alignment, as we will elaborate below, so an edge here should help it win logic customers first. Advanced logic dies are also among the most expensive chips, so logic customers can afford a premium tool. We expect ASML to price its tools at a premium to peers.
我们预计先进逻辑芯片将成为首批采用者。D2W HB 已在逻辑芯片领域实现量产,且该领域的对准要求不断收紧。台积电表示,对于 SoIC 而言,套刻精度“始终是最大的挑战”。随着其 HB 间距到 2029 年从 6 微米缩小至 4.5 微米,对放置精度的要求将进一步收紧。正如下文将详细阐述的那样,ASML 在对准方面具有优势,因此这一优势应有助于其率先赢得逻辑芯片客户。先进逻辑芯片也是成本最高的芯片之一,因此逻辑芯片客户能够承受高端设备的溢价。我们预计 ASML 会将其设备定价为高于竞争对手的水平。
In the next three sections, we discuss (1) the tool’s track system - the most unusual thing about it compared with what is on the market; (2) how ASML’s strengths in alignment, particle control and motion could make its HB tool superior; and (3) the challenges ASML or its supply chain partners still need to resolve to build a working tool. Let’s dive in.
在接下来的三个部分中,我们将讨论:(1) 该工具的轨道系统——与市场上现有产品相比最独特的地方;(2) ASML 在对准、颗粒控制和运动方面的优势如何使其 HB 工具更具优越性;以及 (3) ASML 或其供应链合作伙伴在制造出可用工具之前仍需解决的挑战。让我们深入探讨。
What’s Unique About the Tool
该工具的独特之处
One of the most interesting things about the tool is that it runs on a track. ASML names SuperTrak CONVEYANCE (Fig 3) as an example in its patent filing, so we assume it uses that track and we base our analysis on the track’s published design.
该工具最有趣的一点在于它运行在轨道上。ASML 在其专利申请中将 SuperTrak CONVEYANCE(图 3)列为示例,因此我们假设其使用了该轨道,并基于该轨道的公开设计进行分析。
The fundamental difference from a traditional bonder is where the die lives. In a Besi-type tool, the die is prepared elsewhere, and a bond head picks it up only for the final placement. In ASML’s design, each die sits on its own holder from the moment it leaves the carrier and stays there until the bonding step. The process stations are built around the track: the die stops in front of a station, the station cleans, activates or measures it in place, and the die moves on.
与传统键合机的根本区别在于晶粒(die)的位置。在 Besi 类型的工具中,晶粒在其他地方制备,键合头仅在最终放置时拾取它。而在 ASML 的设计中,每个晶粒从离开载体那一刻起就坐在自己的载具上,直到键合步骤才移动。工艺站围绕轨道构建:晶粒停在某个站点前,该站点就地对其进行清洁、激活或测量,然后晶粒继续移动。
Fig 3: SuperTrak CONVEYANCE track (HORIZON10 platform)
图 3:SuperTrak CONVEYANCE 轨道(HORIZON10 平台)
Source: Company website
来源:公司官网
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