EEBench发布：AI设计电路板的基准测试与模型表现
AI 目前能设计电路板吗？
首次系统化量化AI的硬件工程设计能力，榜单揭示了不同模型在复杂约束下的真实水平，对关注Agent落地物理世界的团队极具参考价值。
We got pretty excited yesterday when OpenAI put a demo of GPT-6 Astra working on a circuit board in KiCad on the front page of its launch post. It is cool to see electronics show up in a major model release like this.
昨天，OpenAI 在其发布帖子的首页展示了 GPT-6 Astra 在 KiCad 电路板上工作的演示，我们对此感到非常兴奋。看到电子工程出现在这样一次重大模型发布中，确实很酷。
We are obviously still some distance from asking an AI to build an entire phone in one prompt. The demo does raise a question we have been thinking about for a while, though: how do we measure whether the electronics an AI produces are actually any good?
显然，我们还远未达到仅用一个提示词就让 AI 构建整部手机的程度。不过，这个演示引发了一个我们思考已久的问题：我们如何衡量 AI 生成的电子设计是否真正优秀？
The models know a surprising amount about electronics
这些模型对电子工程的了解令人惊讶
Our experience has been that current models know much more about electronics than their output in conventional design tools tends to show. They have read textbooks, datasheets, application notes and a lot of code.
我们的经验表明，当前模型对电子工程的了解远超它们在传统设计工具中产出的表现。它们阅读过教科书、数据手册、应用笔记以及大量代码。
You can have an agent operate a graphical CAD tool, but it spends a lot of time clicking around and keeping track of what is on screen. A lot of its context consists of coordinates, menus and application state.
你可以让智能体操作图形化 CAD 工具，但它会花费大量时间四处点击并跟踪屏幕上的内容。它的上下文很大一部分由坐标、菜单和应用程序状态组成。
EEBench uses atopile instead. The circuit lives in declarative code, so the agent can work directly on components, connections and electrical constraints. It can change the design, build it, run a simulation and inspect what failed without leaving the project.
EEBench 使用 atopile。电路以声明式代码形式存在，因此智能体可以直接处理组件、连接和电气约束。它可以在不离开项目的情况下修改设计、构建电路、运行仿真并检查失败原因。
This has worked much better for us than asking a model to draw lines in a GUI. It also means the benchmark can spend less time testing computer use and more time testing electronics.
这比要求模型在 GUI 中绘制线条的效果要好得多。这也意味着基准测试可以将更少的时间用于测试计算机操作，而将更多时间用于测试电子工程能力。
A small part of the starter design for one public EEBench task, in ato v2
EEBench 某个公开任务的入门设计的一小部分，采用 ato v2 格式
.ELEC: @STD::Import {
.project &= "electronics"
.org &= "atopile"
}
.Submission: @type {
.vin: ELEC::ElectricPower
.vhold: ELEC::ElectricPower
.vhold.lv ~ .vin.lv
.c_bank: ELEC::Capacitor {
.capacitance &= 22uF +/- 20%
.max_voltage &= 10V..25V
.temperature_coefficient &= "X5R"
.package &= "0805"
}
.vhold.hv ~> .c_bank ~> .vhold.lv
}.ELEC: @STD::Import {
.project &= "electronics"
.org &= "atopile"
}
.Submission: @type {
.vin: ELEC::ElectricPower
.vhold: ELEC::ElectricPower
.vhold.lv ~ .vin.lv
.c_bank: ELEC::Capacitor {
.capacitance &= 22uF +/- 20%
.max_voltage &= 10V..25V
.temperature_coefficient &= "X5R"
.package &= "0805"
}
.vhold.hv ~> .c_bank ~> .vhold.lv
}The real world is messy
现实世界是混乱的
One of the public tasks is based on a residential energy meter. When its 5 V supply disappears, the circuit has to keep the processor alive for another 20 ms so it can save the accumulated reading. The protected rail must stay above the processor's 3.0 V brownout threshold during that window.
其中一个公开任务基于住宅电表。当 5V 电源消失时，电路必须保持处理器运行另外 20 毫秒，以便保存累积读数。在该时间窗口内，受保护轨的电压必须保持在处理器 3.0V 欠压阈值之上。
Most models intuitively jump to the right base conclusion: add a capacitor.
大多数模型会直觉地得出正确的初步结论：添加一个电容。
A real capacitor makes the task more interesting. A ceramic part may provide much less than its advertised capacitance once it has voltage across it. Parts have tolerances. Adding more capacitance costs more, takes up space and makes the rail slower to recharge when the power returns. A design that works with nominal values can fail with the parts that arrive.
真实的电容使任务变得更加有趣。陶瓷电容在实际施加电压后，其容值可能远低于标称值。元件存在公差。增加更多电容会增加成本、占用空间，并使电源恢复时导轨充电速度变慢。使用标称值设计可行的方案，在实际到货的元件上可能会失效。
EEBench cuts the input power in simulation and measures what happens. It checks the voltage throughout the outage, the effective capacitance at the operating point, the recovery after power returns and the limits on package, dielectric, voltage rating and cost.
EEBench 在仿真中切断输入电源并测量结果。它会检查断电期间的电压、工作点下的有效电容、电源恢复后的情况，以及封装、介质、额定电压和成本的限制。
Saved ngspice output from that submission. The protected rail falls below the 3 V requirement after 0.85 ms.
保存了该提交中的 ngspice 输出。受保护轨在 0.85 毫秒后降至 3 V 要求以下。
Failed power-loss hold-up simulation The protected rail starts near 4.55 volts and falls below the required 3 volt threshold after 0.85 milliseconds, long before the required 20 milliseconds. 05101520 ms 012345 V 3 V minimum fails at 0.85 ms
掉电保持仿真失败。受保护轨从约 4.55 伏开始，在 0.85 毫秒后降至所需的 3 伏阈值以下，远早于所需的 20 毫秒。05101520 ms 012345 V 3 V 最小值在 0.85 ms 处失效
The meter is one of the easier tasks. In a harder analog task, the agent may have to synthesize a multiple-feedback low-pass filter around an op-amp, solve the resistor and capacitor ratios for the required poles, and keep its gain, cutoff frequency and Q inside their limits after every component is pushed to a worst-case tolerance corner. The harness rebuilds the SPICE deck for those corners, runs the AC and transient captures, binds measurements to named probes, and records each result against its lower and upper specification limits.
电表任务是相对容易的任务之一。在更复杂的模拟任务中，智能体可能需要在运算放大器周围综合一个多反馈低通滤波器，求解所需极点的电阻和电容比值，并在每个元件被推至最坏情况容差角时，确保其增益、截止频率和 Q 值保持在限制范围内。测试框架为这些角点重建 SPICE 电路描述文件，运行交流分析和瞬态捕获，将测量值绑定到命名探针，并将每个结果与其上下规格限进行记录对比。
But getting the equations right is only part of electronics engineering. EEBench uses real manufacturer parts, with specifications extracted from their datasheets and carried into the SPICE model. The agent has to find a combination that works across those tolerance corners while also choosing parts that exist, can be ordered and are reasonably priced for the product. That trade-off between electrical performance, cost and supply is much closer to designing real hardware than picking ideal values from a textbook.
但正确列出方程只是电子工程的一部分。EEBench 使用真实的制造商元器件，其规格从数据表中提取并带入 SPICE 模型。智能体必须找到能在这些容差角下工作的组合，同时选择现有、可订购且对产品而言价格合理的器件。这种电气性能、成本和供应之间的权衡，比从教科书中挑选理想值更接近真实硬件的设计。
This is the part we find most interesting, because it is what electrical engineering eventually boils down to, just like every other engineering discipline: trade-offs.
这是我们认为最有趣的部分，因为正如其他所有工程学科一样，电气工程最终归结为：权衡。
How the grading works
评分机制如何运作
EEBench checks are fully deterministic. It builds the submitted design, constructs the circuit graph and bill of materials, and runs a set of SPICE simulations and design checks. Each requirement produces a measurement with a limit.
EEBench 检查是完全确定性的。它构建提交的电路设计，构造电路图与物料清单（BOM），并运行一组 SPICE 仿真与设计检查。每项要求都会产生带有极限值的测量结果。
For the energy-meter task, the harness measures the protected rail while the input drops out and returns. Other tasks measure gain, thresholds, ripple, transient response and behavior at component-tolerance corners. The technical score is combined with cost efficiency against a reference bill of materials. Cost only helps once the circuit works.
对于电能表任务，测试框架在输入跌落和恢复期间测量受保护轨。其他任务则测量增益、阈值、纹波、瞬态响应以及元件容差角下的行为。技术得分会与参考物料清单的成本效率相结合。只有当电路正常工作后，成本才会产生影响。
This is similar to giving a coding agent a compiler and tests, except the tests are measuring voltages and component behavior..
这类似于给代码智能体提供编译器和测试用例，只不过这里的测试是在测量电压和元件行为。
EEBench V1 covers analog and digital design through simulation. It does not yet tell us whether a model can lay out, manufacture and bring up a complete product. We want to add those parts later. The current benchmark concentrates on the requirements, design and verification loop because that is where we can already grade useful engineering work objectively. The full methodology and sample result explorer are public.
EEBench V1 涵盖通过仿真进行的模拟和数字设计。它尚未告诉我们一个模型是否能够完成布局、制造并调试出完整的产品。我们打算稍后添加这些部分。当前的基准测试集中于需求、设计和验证循环，因为这是我们能够客观评估有用工程工作的地方。完整的方法论和示例结果浏览器是公开的。
What we are seeing on the leaderboard
我们在排行榜上看到的内容
The September 1 results are encouraging. Claude Opus 5 scored 61.6% across the 13 tasks in EEBench V1. Grok 4.6 came second at 57.1%, just ahead of Claude Fable 5.1 at 56.4%. A few months ago we would not have expected models to do this well.
9月1日的结果令人鼓舞。Claude Opus 5 在 EEBench V1 的 13 项任务中得分 61.6%。Grok 4.6 以 57.1% 的成绩排名第二，略高于 Claude Fable 5.1 的 56.4%。几个月前，我们不会预料到模型能取得这样的成绩。
1Claude Opus 561.6%
1 Claude Opus 5 61.6%
2Grok 4.657.1%
2 Grok 4.6 57.1%
3Claude Fable 5.156.4%
3 Claude Fable 5.1 56.4%
4Claude Fable 554.3%
4 Claude Fable 5 54.3%
5Claude Opus 4.8 Max51.4%
5 Claude Opus 4.8 Max 51.4%
See the full leaderboard and run details
查看完整的排行榜和运行详情
There was another result we were especially happy to see: xAI included EEBench in the Grok 4.6 model card. It appears in the section on “engineering acceleration,” alongside evaluations for 3D modeling and parametric CAD. Their published run put Grok 4.6 at 60.0% with xhigh reasoning effort. Seeing a frontier lab use EEBench to describe a new model's engineering ability makes us think this is becoming a category people care about.
我们还特别高兴看到另一个结果：xAI 将 EEBench 包含在 Grok 4.6 的模型卡片中。它出现在“工程加速”部分，与 3D 建模和参数化 CAD 的评估并列。他们发布的运行结果显示，在高推理强度下，Grok 4.6 得分为 60.0%。看到前沿实验室使用 EEBench 来描述新模型的工程能力，让我们认为这正成为一个人们关心的类别。
Anthropic's models have consistently done well in this environment. Grok's rise is also interesting. In its Grok 4.6 launch post, xAI says the model received high-quality engineering data and RL training in domain-specific environments including computer-aided design. Its EEBench result fits that story.
Anthropic 的模型在这个环境中一直表现良好。Grok 的崛起也很有趣。在其 Grok 4.6 发布文章中，xAI 表示该模型接收了高质量的工程数据和领域特定环境（包括计算机辅助设计）中的强化学习训练。其 EEBench 的结果符合这一说法。
The OpenAI models we have tested so far sit further down the table. GPT-5.5 scored 42.3%, while GPT-5.6 Sol scored 39.4%. We do not have a GPT-6 Astra result yet. After seeing it work on a board in KiCad, we would really like to find out how it handles these circuit-design tasks.
我们目前测试过的 OpenAI 模型排名较靠后。GPT-5.5 得分为 42.3%，而 GPT-5.6 Sol 得分为 39.4%。我们还没有 GPT-6 Astra 的结果。在看到它在 KiCad 的电路板上工作后，我们非常想了解它是如何处理这些电路设计任务的。
Training environment
训练环境
Once we had a simulation harness that could grade a circuit, we also had the beginnings of an RL environment for electronics. The same checks can be used as reward signals during post-training.
一旦我们拥有了能够对电路进行评分的仿真框架，我们就有了用于电子学的强化学习环境的基础。相同的检查可以在后训练期间用作奖励信号。
A failed run contains useful information. We can see which voltage missed its limit, which operating corner failed, or whether the model solved the problem with an unnecessarily expensive design. That gives a training loop more to work with than a model saying that a schematic looks plausible.
失败的运行包含有用的信息。我们可以看到哪个电压超出了限制，哪个工作角点失败，或者模型是否用不必要的高成本设计解决了问题。这为训练循环提供了比模型声称原理图看起来合理更多的素材。
EEBench is the small, public view of this work. We are also starting to work directly with frontier labs that want to make their models better at electronics. If you work on evals or post-training, you can talk to us about the larger evaluation suites and simulation-backed training environments we provide.
EEBench 是这项工作的公开小型展示。我们也在开始直接与那些希望提升其模型电子领域能力的顶尖实验室合作。如果您从事评估或后训练工作，可以与我们探讨我们提供的大型评估套件及仿真支持的训练环境。
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