CPU GPU TPU NPU LPU 五大 AI 硬件架构对比解析
CPU vs GPU vs TPU vs NPU vs LPU, explained visually:
CPU vs GPU vs TPU vs NPU vs LPU, explained visually:
CPU、GPU、TPU、NPU 与 LPU，图解说明：
(bookmark this)
（收藏此内容）
5 hardware architectures power AI today.
5 种硬件架构支撑着当今的 AI。
Each one makes a fundamentally different tradeoff between flexibility, parallelism, and memory access.
它们在灵活性、并行性和内存访问之间做出了根本不同的权衡。
> CPU
> CPU
It is built for general-purpose computing. A few powerful cores handle complex logic, branching, and system-level tasks.
它专为通用计算而设计。少数强大的核心处理复杂的逻辑、分支和系统级任务。
It has deep cache hierarchies and off-chip main memory (DRAM). It's great for operating systems, databases, and decision-heavy code, but not that great for repetitive math like matrix multiplications.
它具有深层缓存层次结构和片外主存（DRAM）。它在操作系统、数据库和决策密集型代码方面表现出色，但在矩阵乘法等重复性数学运算方面表现不佳。
> GPU
> GPU
Instead of a few powerful cores, GPUs spread work across thousands of smaller cores that all execute the same instruction on different data.
与少数强大核心不同，GPU 将工作分散到数千个较小的核心上，这些核心对不同的数据执行相同的指令。
This is why GPUs dominate AI training. The parallelism maps directly to the kind of math neural networks need.
这就是为什么 GPU 在 AI 训练中占据主导地位。这种并行性直接映射到神经网络所需的数学运算类型。
> TPU
> TPU
They go one step further with specialization.
它们通过专业化更进一步。
The core compute unit is a grid of multiply-accumulate (MAC) units where data flows through in a wave pattern.
核心计算单元是一个乘加（MAC）单元网格，数据以波浪模式流动。
Weights enter from one side, activations from the other, and partial results propagate without going back to memory each time.
权重从一侧进入，激活值从另一侧进入，部分结果在传播时不需要每次都返回内存。
The entire execution is compiler-controlled, not hardware-scheduled. Google designed TPUs specifically for neural network workloads.
整个执行过程由编译器控制，而非硬件调度。Google 专门针对神经网络负载设计了 TPU。
> NPU
> NPU
This is an edge-optimized variant.
这是一种面向边缘优化的变体。
The architecture is built around a Neural Compute Engine packed with MAC arrays and on-chip SRAM, but instead of high-bandwidth memory (HBM), NPUs use low-power system memory.
其架构围绕神经计算引擎构建，该引擎集成了 MAC 阵列和片上 SRAM，但 NPU 不使用高带宽内存（HBM），而是使用低功耗系统内存。
The design goal is to run inference at single-digit watt power budgets, like smartphones, wearables, and IoT devices.
设计目标是以个位数瓦特的功耗预算运行推理，例如智能手机、可穿戴设备和物联网设备。
Apple Neural Engine and Intel's NPU follow this pattern.
Apple Neural Engine 和 Intel 的 NPU 遵循这一模式。
> LPU (Language Processing Unit)
> LPU（语言处理单元）
This is the newest entrant, by Groq.
这是最新的入场者，由 Groq 推出。
The architecture removes off-chip memory from the critical path entirely. All weight storage lives in on-chip SRAM.
该架构完全将片外内存从关键路径中移除。所有权重存储都位于片上 SRAM 中。
Execution is fully deterministic and compiler-scheduled, which means zero cache misses and zero runtime scheduling overhead.
执行是完全确定性的且由编译器调度，这意味着零缓存未命中和零运行时调度开销。
The tradeoff is that it provides limited memory per chip, which means you need hundreds of chips linked together to serve a single large model. But the latency advantage is real.
其权衡在于每个芯片提供的内存有限，这意味着你需要将数百个芯片链接在一起才能服务于单个大型模型。但延迟优势是实实在在的。
AI compute has evolved from general-purpose flexibility (CPU) to extreme specialization (LPU). Each step trades some level of generality for efficiency.
AI 计算已从通用灵活性（CPU）演变为极致专业化（LPU）。每一步都以牺牲一定的通用性为代价来换取效率。
The visual below maps the internal architecture of all five side by side.
下图并列展示了这五种架构的内部结构。
To dive deeper into GPU specifically, Akshay wrote a detailed article on it.
若要更深入地了解 GPU，Akshay 为此撰写了一篇详细文章。
It builds up from first principles why memory and compute compete, why that gap exists in the hardware, and what makes a workload memory-bound in the first place.
它从第一性原理出发，解释了为什么内存和计算会相互竞争、硬件中为何存在这种差距，以及工作负载在根本上为何受限于内存。
Read it below.
请阅读下文。
更进一步：量化金融体系
看懂新闻只是起点——沿量化金融路径，把它变成能交付的工程能力